/*
 * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
 *
 * Permission to use, copy, modify, and/or distribute this software for
 * any purpose with or without fee is hereby granted, provided that the
 * above copyright notice and this permission notice appear in all
 * copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
 * PERFORMANCE OF THIS SOFTWARE.
 */

///////////////////////////////////////////////////////////////////////////////////////////////
//
// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq  3.1 12/1/2017 
// User Name:gunjans
//
// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
//
///////////////////////////////////////////////////////////////////////////////////////////////

#ifndef __WFSS_CE_REG_SEQ_REG_H__
#define __WFSS_CE_REG_SEQ_REG_H__

#include "seq_hwio.h"
#include "wfss_ce_reg_seq_hwiobase.h"
#ifdef SCALE_INCLUDES
	#include "HALhwio.h"
#else
	#include "msmhwio.h"
#endif


///////////////////////////////////////////////////////////////////////////////////////////////
// Register Data for Block WFSS_CE_CHANNEL_DST_REG
///////////////////////////////////////////////////////////////////////////////////////////////

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x)       (x+0x00000000)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x)       (x+0x00000000)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK          0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT                   0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x)       (x+0x00000004)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x)       (x+0x00000004)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK          0x00ffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT                   0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x)             (x+0x00000008)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x)             (x+0x00000008)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT                         0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK     0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT            0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x)         (x+0x0000000c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x)         (x+0x0000000c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK            0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT                     0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)           \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val)     \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x)           (x+0x00000010)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x)           (x+0x00000010)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK              0x003fffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT                       0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT        0xe

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT        0xc

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT        0x7

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK  0x00000040
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT         0x6

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT        0x3

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT        0x2

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x)    (x+0x0000001c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x)    (x+0x0000001c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK       0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT                0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x)    (x+0x00000020)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x)    (x+0x00000020)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK       0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT                0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x)  (x+0x00000048)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x)  (x+0x00000048)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK     0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT              0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x)  (x+0x0000004c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x)  (x+0x0000004c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK     0x000001ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT              0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x)      (x+0x00000050)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x)      (x+0x00000050)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK         0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT                  0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val)  \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK   0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT          0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK   0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT            0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x)     (x+0x00000058)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x)     (x+0x00000058)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK        0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT                 0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)       \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x)     (x+0x0000005c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x)     (x+0x0000005c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK        0x00ffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT                 0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)       \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x)           (x+0x00000060)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x)           (x+0x00000060)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK              0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT                       0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK      0x0000ff00
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT             0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK   0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT          0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x)       (x+0x00000064)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x)       (x+0x00000064)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK          0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT                   0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x)         (x+0x00000068)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x)         (x+0x00000068)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK            0x03ffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT                     0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)           \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val)     \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK   0x03c00000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT         0x16

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT        0xe

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT        0xc

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT        0x7

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT        0x6

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT        0x3

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT        0x2

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x)  (x+0x0000006c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x)  (x+0x0000006c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK     0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT              0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x)  (x+0x00000070)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x)  (x+0x00000070)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK     0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT              0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK   0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT            0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK   0x000001ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT            0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x)    (x+0x000000a8)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x)    (x+0x000000a8)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK       0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT                0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x)                (x+0x000000b0)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x)                (x+0x000000b0)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                   0x0001ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT                            0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK   0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT          0x0

//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x)             (x+0x000000b4)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x)             (x+0x000000b4)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                0x0000003f
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT                         0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK        0x00000020
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT               0x5

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT        0x4

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT        0x3

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK     0x00000004
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT            0x2

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK     0x00000002
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT            0x1

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK        0x00000001
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT               0x0

//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 ////

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x)         (x+0x000000b8)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x)         (x+0x000000b8)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK            0x0000000f
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT                     0
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)           \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask)    \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val)     \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT        0x3

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT        0x2

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT        0x1

#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK   0x00000001
#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT          0x0

//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP ////

#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x)             (x+0x00000400)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x)             (x+0x00000400)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT                         0
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK       0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT              0x0

//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP ////

#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x)             (x+0x00000404)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x)             (x+0x00000404)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT                         0
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK       0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT              0x0

//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP ////

#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x)           (x+0x00000408)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x)           (x+0x00000408)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK              0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT                       0
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK     0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT            0x0

//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP ////

#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x)           (x+0x0000040c)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x)           (x+0x0000040c)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK              0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT                       0
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK     0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT            0x0


///////////////////////////////////////////////////////////////////////////////////////////////
// Register Data for Block WFSS_CE_CHANNEL_SRC_REG
///////////////////////////////////////////////////////////////////////////////////////////////

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x)        (x+0x00000000)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x)        (x+0x00000000)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK           0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT                    0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)          \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask)   \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val)    \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x)        (x+0x00000004)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x)        (x+0x00000004)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK           0x00ffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT                    0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)          \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask)   \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val)    \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x)              (x+0x00000008)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x)              (x+0x00000008)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT                          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK      0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT             0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x)          (x+0x0000000c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x)          (x+0x0000000c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK             0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT                      0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)            \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask)     \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val)      \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x)            (x+0x00000010)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x)            (x+0x00000010)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK               0x003fffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT                        0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)              \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask)       \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val)        \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT        0xe

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT        0xc

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK  0x00000080
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT         0x7

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK   0x00000040
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT          0x6

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK  0x00000008
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT         0x3

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK  0x00000004
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT         0x2

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x)     (x+0x0000001c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x)     (x+0x0000001c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK        0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT                 0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)       \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x)     (x+0x00000020)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x)     (x+0x00000020)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK        0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT                 0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)       \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x)   (x+0x00000048)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x)   (x+0x00000048)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK      0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT               0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)     \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x)   (x+0x0000004c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x)   (x+0x0000004c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK      0x000001ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT               0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)     \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x)       (x+0x00000050)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x)       (x+0x00000050)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK          0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT                   0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK    0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT           0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK    0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT             0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)   \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x)                 (x+0x00000058)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x)                 (x+0x00000058)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                    0x0000001f
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT                             0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)                   \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask)            \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val)             \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val)      \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK          0x00000010
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                 0x4

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK      0x00000008
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT             0x3

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK           0x00000004
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                  0x2

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK        0x00000002
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT               0x1

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT        0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x)             (x+0x0000005c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x)             (x+0x0000005c)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                0x0000001f
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT                         0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK        0x00000010
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT               0x4

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT        0x3

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT        0x2

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK     0x00000002
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT            0x1

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK        0x00000001
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT               0x0

//// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x)              (x+0x00000060)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x)              (x+0x00000060)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                 0xffffffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT                          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK          0xffff0000
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                0x10

#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK           0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                  0x0

//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x)              (x+0x00000400)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x)              (x+0x00000400)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT                          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK        0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT               0x0

//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP ////

#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x)              (x+0x00000404)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x)              (x+0x00000404)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                 0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT                          0
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) 
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val)
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK        0x0000ffff
#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT               0x0


///////////////////////////////////////////////////////////////////////////////////////////////
// Register Data for Block WFSS_CE_COMMON_REG
///////////////////////////////////////////////////////////////////////////////////////////////

//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x)              (x+0x00000000)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x)              (x+0x00000000)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK                 0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT                          0
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK           0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT                  0x0

//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x)              (x+0x00000004)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x)              (x+0x00000004)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK                 0x000000ff
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT                          0
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK           0x000000ff
#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT                  0x0

//// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x)             (x+0x00000008)
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x)             (x+0x00000008)
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK                0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT                         0
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT        0x9

#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT        0x4

#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f
#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK ////

#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x)          (x+0x0000000c)
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x)          (x+0x0000000c)
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK             0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT                      0
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)            \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask)     \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val)      \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE ////

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x)         (x+0x00000010)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x)         (x+0x00000010)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK            0x80000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT                     0
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask)    \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val)     \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT       0x1f

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK      0x00000800
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT             0xb

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK   0x00000400
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT          0xa

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK    0x00000200
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT           0x9

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT        0x8

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT        0x7

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT        0x6

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT        0x5

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT        0x4

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT        0x3

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT        0x2

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK     0x00000002
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT            0x1

#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK       0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT              0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x)               (x+0x00000014)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x)               (x+0x00000014)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK                  0x01010101
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT                           0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)                 \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask)          \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val)           \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT       0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT        0x8

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x)              (x+0x00000018)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x)              (x+0x00000018)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK                 0x003f3f3f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT                          0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)                \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask)         \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val)          \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val)   \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT        0x8

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x)        (x+0x0000001c)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x)        (x+0x0000001c)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK           0xffff3f3f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT                    0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)          \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask)   \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val)    \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x)        (x+0x00000020)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x)        (x+0x00000020)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK           0xffff3f3f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT                    0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)          \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask)   \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val)    \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x)           (x+0x00000024)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x)           (x+0x00000024)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK              0x0fffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT                       0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT       0x1b

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT       0x1a

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT       0x19

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT       0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT       0x17

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT       0x14

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT       0x11

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x)           (x+0x00000028)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x)           (x+0x00000028)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK              0xffff0001
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT                       0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x)            (x+0x0000002c)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x)            (x+0x0000002c)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK               0x0000ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT                        0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)              \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask)       \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val)        \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS ////

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x)          (x+0x00000030)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x)          (x+0x00000030)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK             0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT                      0
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)            \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask)     \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val)      \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT        0x0

//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x)                  (x+0x00000034)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x)                  (x+0x00000034)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK                     0x01ffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT                              0
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)                    \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val)              \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK             0x01000000
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT                   0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK         0x00fff000
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT                0xc

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK         0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT                0x0

//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x)                  (x+0x00000038)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x)                  (x+0x00000038)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK                     0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT                              0
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)                    \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val)              \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK         0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT                0x0

//// Register WFSS_CE_COMMON_R0_CE_SECURITY ////

#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x)                   (x+0x0000003c)
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x)                   (x+0x0000003c)
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK                      0x00ffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT                               0
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)                     \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask)              \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val)               \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK                 0x00fff000
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT                        0xc

#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK                  0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT                         0x0

//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x)                (x+0x00000040)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x)                (x+0x00000040)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK                   0x01ffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK           0x01000000
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT                 0x18

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK       0x00fff000
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT              0xc

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK       0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT              0x0

//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x)                (x+0x00000044)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x)                (x+0x00000044)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK                   0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK       0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT              0x0

//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x)       (x+0x00000048)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x)       (x+0x00000048)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK          0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT                   0
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK   0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT          0x0

//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x)       (x+0x0000004c)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x)       (x+0x0000004c)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK          0x0001ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT                   0
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)         \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask)  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val)   \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK   0x0001ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT          0x0

//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x)            (x+0x00000050)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x)            (x+0x00000050)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK               0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_SHFT                        0
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)              \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, mask)       \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, val)        \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK        0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT               0x0

//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x)            (x+0x00000054)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x)            (x+0x00000054)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK               0x0001ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_SHFT                        0
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)              \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, mask)       \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, val)        \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK        0x0001ffff
#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT               0x0

//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x)                (x+0x00000058)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x)                (x+0x00000058)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK             0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT                    0x0

//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x)                (x+0x0000005c)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x)                (x+0x0000005c)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK             0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT                    0x0

//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x)                (x+0x00000060)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x)                (x+0x00000060)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK             0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT                    0x0

//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 ////

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x)                (x+0x00000064)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x)                (x+0x00000064)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK             0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT                    0x0

//// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS ////

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x)               (x+0x00000068)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x)               (x+0x00000068)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK                  0xfffdffff
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT                           0
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)                 \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask)          \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val)           \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val)    \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK       0x80000000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT             0x1f

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK  0x40000000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT        0x1e

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK      0x3ffc0000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT            0x12

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK           0x00010000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT                 0x10

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK          0x0000f000
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT                 0xc

#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK     0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT            0x0

//// Register WFSS_CE_COMMON_R0_CE_IDLE_CONFIG ////

#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x)                (x+0x0000006c)
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x)                (x+0x0000006c)
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK                   0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK          0x00000fff
#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT                 0x0

//// Register WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR ////

#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x)           (x+0x00000070)
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_PHYS(x)           (x+0x00000070)
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK              0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_SHFT                       0
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_RMSK)
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_INM(x, mask)      \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUT(x, val)       \
	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_BMSK        0xffffffff
#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ADDR_VALUE_SHFT               0x0

//// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL ////

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x)                  (x+0x00000400)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x)                  (x+0x00000400)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK                     0x000100ff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT                              0
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)                    \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val)              \
	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x00010000
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT       0x10

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK  0x000000ff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT         0x0

//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 ////

#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x)                (x+0x00000404)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x)                (x+0x00000404)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK              0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT                     0x0

//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 ////

#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x)                (x+0x00000408)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x)                (x+0x00000408)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK                   0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT                            0
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)                  \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask)           \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val)            \
	out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val)     \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK              0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT                     0x0

//// Register WFSS_CE_COMMON_R1_TESTBUS_LOW ////

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x)                   (x+0x0000040c)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x)                   (x+0x0000040c)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK                      0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT                               0
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)                     \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask)              \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val)               \
	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val)        \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK                  0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT                         0x0

//// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH ////

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x)                  (x+0x00000410)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x)                  (x+0x00000410)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK                     0x000000ff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT                              0
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)                    \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask)             \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val)              \
	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val)       \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK                 0x000000ff
#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT                        0x0

//// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL ////

#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)     (x+0x00000414)
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x)     (x+0x00000414)
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK        0xffffffff
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT                 0
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)       \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \
	out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT       0x11

#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT        0x2

#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT        0x1

#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT        0x0

//// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK ////

#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x)             (x+0x00000418)
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x)             (x+0x00000418)
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK                0x00000001
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT                         0
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)               \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK)
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask)        \
	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val)         \
	out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val)
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)  \
	do {\
		HWIO_INTLOCK(); \
		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \
		HWIO_INTFREE();\
	} while (0) 

#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0


///////////////////////////////////////////////////////////////////////////////////////////////
// Register Data for Block WFSS_CE_REG
///////////////////////////////////////////////////////////////////////////////////////////////


#endif

